isham research
Hiway joins Freeway and Subway?
(Things have changed a little since this was written. If you've read it before, see the notes.)
IBM's next medium-sized zSeries mainframe - Subway - will be built by Hitachi and will use a five-way MCM to deliver one to four processors for customer use. A decent I/O subsystem - still with configuration limitations - OSAs, and better I/O for Linux are also on the cards.
IBM is supplying the processor chips out of its Freeway (z900) range. Since the new system is also intended for marketing under the Hitachi name in the Japanese VOS3 domestic market, IBM has had to restore the VOS3 functionality it deleted in the original G7 - a good opportunity to fix a few other bugs. Such a rework ('G7-2') would usually introduce a small performance gain derived from technology improvements since the original G7 shipped, but IBM appears to have decided not to market this as a midlife kicker for Freeway at this time.
It's entirely possible that Hitachi have told us just what IBM's Subway will look like - although in typical fashion, only in Japanese. And, as they say - watashitachi wa Nihhongo no hanashimasen. But does this matter these days?1
A recent IBM commercial promised simultaneous translation of telephone conversations. It's much easier if the data is already machine readable. Like on a web page:
URL 1 - http://www.hitachi.co.jp/Prod/comp/Mparallel/HARD/jpn/ap80/ap_lineup.html
URL 2 - http://www.hitachi.co.jp/Prod/comp/Mparallel/HARD/jpn/ap80/ap_tco_4.html
These are Hitachi's new (domestic market ONLY) 64-bit mainframes, built using IBM's G7-2 Freeway chip. But how much does either of them resemble Subway?
This is fascinating. Translation of URL 1 produces a table of configuration possibilities in two columns. Leaving aside some obvious glitches in the translation and converting Hitachi's domestic terminology (ACONARC = ESCON, FIBARC = FICON, etc) the first column seems to correspond very well with what is already known about Subway. The second column is very interesting.
|
Model |
100, 120, 140, 150, 160, |
185, 215, 315, 415, |
|
Maximum memory capacity |
16GB |
32GB |
|
Memory increment |
512MB |
512MB |
|
I/O Processors |
1-4 |
1-8 |
|
Maximum channels |
256 |
512 |
|
Maximum parallel channels |
96 |
192 |
|
Maximum ESCON channels |
256 |
512 |
|
Maximum FICON channels |
36 |
72 |
|
Maximum LAN Adaptors |
16 |
32 |
|
Maximum coupling links |
16 |
32 |
|
Data compression feature |
Standard |
Standard |
|
Integrated database processor |
Optional |
Optional |
|
Integrated cryptographic processor |
Optional |
Optional |
|
Integrated Linux feature |
Optional |
Optional |
|
IEEE Floating Point (?) |
Standard |
Standard |
|
Multiple Systems Facility |
Optional |
Optional |
|
Energy conservation class |
A |
A |
The model numbering is standard - the first digit is the number of processors and the last indicates a technology level. At first glance, it seems that models 185-815 represent 'dyadics' - two-sided machines using two MCMs. Everything adds up, except that it would require one processor to be available as a spare to both sides - quite difficult technically. Memory bandwidth might also be an issue.
URL 2 comes to our aid, first with the assertion that only one MCM is ever used, and secondly with a photograph of an open MCM clearly showing it to be fully populated.
So the conclusion is - column 1 represents the future Subway and column 2 something different - perhaps IBM's z900 Model 101 to 109 MCM adapted for the Japanese domestic market. We can't call it 'Freeway' but how about 'Hiway'? One further point - the graphic on URL 1 clearly shows the 185, 215 and 315 as more powerful than their Subway equivalents. Is all of this due to memory bandwidth, or is Hitachi using the G7-2 chip at 'turbo' speed - perhaps to compensate for bottlenecks in the fully populated system? IBM's larger MCM has better cooling provision, after all.
Performance is as yet unclear. In a less well cooled environment, processor chips cannot be run at the same clock speeds that can be used in better environments. A base processor speed around 190 MIPS would yield perhaps 80 to 625 or so MIPS across the range in production - although a UK audience was told on 27 October 2001 that Subway would go all the way down to 50 MIPS.
It now seems likely that IBM will announce this system in mid-February 2002 for shipment just before the end of 2Q02.
Software charging may prove an interesting issue. As a successor to the Multiprise 3000, Subway might be expected to have some form of preferential software charging - Multiprise costs roughly half the price/MIPS compared with other systems of similar capacity. Hitachi's announced version of Subway seems to have Coupling Links - and a GOLC (or NALC) machine cannot currently be part of a Parallel Sysplex. Some solution permitting MSU consolidation in a Sysplex seems likely - perhaps advantageous MSU definitions? This would have the great advantage of simplicity - the current GOLC scheme is bad enough where products have no GOLC definitions are are thus priced by groups, but it becomes a nightmare when used fractionally in emulation situations.
As things stand, Hitachi will not market either product outside its VOS market and this situation is very unlikely to change.